The so-called “silicon revolution” brought about the development of faster and larger computers beginning in the early 1960's with predictions of rapid growth because of the increasing numbers of transistors packed into integrated circuits with estimates they would double every two years. Since 1975, however, they doubled about every 18 months.
An active period of innovation in the 1970's followed in the areas of circuit design, chip architecture, design aids, processes, tools, testing, manufacturing architecture, and manufacturing discipline. The combination of these disciplines brought about the VLSI era and the ability to mass-produce chips with 100,000 transistors per chip at the end of the 1980's, succeeding the large scale Integration (“LSI”) era of the 1970's with only 1,000 transistors per chip. (Carre, H. et al. “Semiconductor Manufacturing Technology at IBM”, IBM J. RES. DEVELOP., VOL 26, no. 5, September 1982). Mescia et al. also describe the industrial scale manufacture of these VLSI devices. (Mescia, N. C. et al. “Plant Automation in a Structured Distributed System Environment,” IBM J. RES. DEVELOP., VOL 26, no. 4, July 1982).
The release of IBM's Power6™ chip in 2007, noted “miniaturization has allowed chipmakers to make chips faster by cramming more transistors on a single slice of silicon, to the point where high-end processors have hundreds of millions of transistors. But the process also tends to make chips run hotter, and engineers have been trying to figure out how to keep shrinking chips down while avoiding them frying their own circuitry.” (http://www.nytimes.com/reuters/technology/tech-ibm-power.html?pagewanted=print (2/7/2006))
Technology scaling of semiconductor devices to 90 nm and below has provided many benefits in the field of microelectronics, but has introduced new considerations as well. While smaller chip geometries result in higher levels of on-chip integration and performance, higher current and power densities, increased leakage currents, and low-k dielectrics with poorer heat conductivity occur that present new challenges to package and heat dissipation designs.
CMOS power density is increasing. Recently the industry has seen it rise from 100 W/sq cm to 200 W/sq cm, beyond that of bipolar technology in the early 1990's. This increase in power density also increases the operating temperature of the device which materially interfered with proper operation of the device. The industry addressed this increase in operating temperature by securing the device to a heat exchange structure or material (i.e., heat spreader), but different coefficients of expansion of the heat spreader and the device caused structural and consequently further operating problems in the device. The difficulty was resolved for the most part by placing a TIM between the two that not only joined them in a heat exchange relation but also provided sufficient flexibility that enabled a link between the surfaces that substantially compensated for their different coefficients of expansions and substantially minimized any stress or strain placed on the device in the heat exchange process. The TIM material typically would sit underneath “contact patches,” helping to thermally bridge the gap between the device being cooled and the “contact patch.”
New generation servers employ more vendor technology that usually requires some level of custom integration to realize reliable performance. “VTM” (voltage transmission module) is one such technology used for power control in servers developed today. Kim, et al., U.S. Pat. Nos. 8,498,540 and 8,565,606 describe circuits used in voltage transmission module technology. The VTM requires a TIM to effectively transfer heat from an array of VTMs to a common heat spreader. Inherent in manufacturing a VTM printed circuit board (PCB) assembly is rework. Thus, the common heat spreader must be easily separable from the VTM array in order to remove and replace a failed module. The heat spreader removal process must not damage any good modules.
The VTM has fragile solder connections that can only tolerate a compressive limit of about 15 psi and about 7 psi of tensile stress. TIMs that separate at tensile stress less than 7 psi either lack compliance to accommodate the bondline tolerances as in the case of thermal pads; or, in the case of accommodating bondline tolerances, for example greases or low cross link density gels, lack positional stability and pump out due to thermal mechanical movement between the common heat spreader and large PCB with the array of modules. Curable paste, adhesive TIMs that accommodate bondline tolerances and which are mechanically stable will require tensile forces greater than 7 psi to separate and thus will damage good components.
The application requirements for thermal interface materials therefore can include both assembly (compressive) and disassembly (tensile) force requirements. As noted above, the VTM module has a compressive limit of about 15 psi and tensile limit of about 7 psi. These requirements have limited the selection of thermal interface materials in the past to only one candidate, Chomerics T636, however, the present invention allows the use of many other commercial TIM's as well as newly formulated TIM's.
The present invention proposes a method for controlling TIM force for disassembly which would meet this and all other application requirements.